SH7040 Datasheet, PDF (477/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

(25) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and
Operation is Restarted in Normal Mode: Figure 12.121 shows an explanatory diagram of the
case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal
mode after re-setting.
MTU output
1
2
3
4
RESET TOCR TMDR TOER
(CPWM) (1)
5
PFC
(MTU)
6
TSTR
(1)
7
8
9
10
11
12
Match Error PFC TSTR TMDR TIOR
occurs (PORT) (0) (normal) (1 init
0 out)
13
PFC
(MTU)
14
TSTR
(1)
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
PE9
High-Z
High-Z
PE11
High-Z
Figure 12.121 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with
TOCR.
3. Set reset-synchronous PWM.
4. Enable channel 3 and 4 output with TOER.
5. Set MTU output with the PFC.
6. The count operation is started by TSTR.
7. The reset-synchronous PWM waveform is output on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR. (MTU output becomes the reset-synchronous PWM
output initial value.)
11. Set normal operating mode. (MTU positive phase output is low, and negative phase output is
high.)
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
439