SH7040 Datasheet, PDF (323/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Bit 4: Bit 3:
CKEG1 CKEG0 Description
0
0
Count on rising edges (initial value)
1
Count on falling edges
1
X
Count on both rising and falling edges
Notes: 1. X: 0 or 1, don’t care.
2. Internal clock edge selection is effective when the input clock is φ/4 or slower. When ø/1
or the overflow/underflow of another channel is selected for the input clock, although
values can be written, counter operation complies with the initial value (count on rising
edges).
• Bits 2–0—Timer Prescaler 2–0 (TPSC2–TPSC0): TPSC2–TPSC0 select the counter clock
source for the TCNT. An independent clock source can be selected for each channel. Table
12.4 shows the possible settings for each channel.
Table 12.4 MTU Clock Sources
Internal Clock
Chan-
φ/ φ/ φ/
nel φ/1 φ/4 16 64 256
0
O OO
O
X
1
O OO
O
O
2
O OO
O
X
3
O OO
O
O
4
O OO
O
O
Note: Symbols: O: Setting possible
φ/
1024
Other Channel
Overflow/
Underflow
X
X
X
O
O
X
O
X
O
X
X: Setting not possible
External Clock
TCL TCL TCL TCL
KA KB KC KD
O OO O
O OX X
O OO X
O OX X
O OX X
Channel 0:
Bit 2: Bit 1:
TPSC2 TPSC1
0
0
1
1
0
1
Bit 0:
TPSC0
0
1
0
1
0
1
0
1
Description
Internal clock: count with φ/1 (initial value)
Internal clock: count with φ/4
Internal clock: count with φ/16
Internal clock: count with φ/64
External clock: count with the TCLKA pin input
External clock: count with the TCLKB pin input
External clock: count with the TCLKC pin input
External clock: count with the TCLKD pin input
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