SH7040 Datasheet, PDF(445/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (445/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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12.7.16 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is

not set and TCNT clearing takes precedence.

Figure 12.93 shows the operation timing when a TGR compare-match is specified as the clearing

source, and H'FFFF is set in TGR.

Ï

TCNT input

clock

TCNT

Counter clear

signal

H'FFFF

H'0000

TGF flag

TCFV flag

Disabled

Figure 12.93 Contention between Overflow and Counter Clearing

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