SH7040 Datasheet, PDF (197/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 9.2 Special Cache Space
Space Classification
Address array
Data array
Address
H'FFFFF000–H'FFFFF3FF
H'FFFFF400–H'FFFFF7FF
Size
1 kbyte
1 kbyte
Bus Width
32 bit
32 bit
9.3.1 Cache Address Array Read/Write Space
The cache address array has a compulsory read/write (figure 9.3).
31
10 9
21 0
Upper 22 bits of the address array space address
Address
(22 bits)
Entry address
–
(8 bits)
(2 bits)
31
26 25 24
Data
–
(6 bits)
Tag address
(15 bits)
10 9
0
–
(10 bits)
Valid bit (1 bit)
Figure 9.3 Cache Address Array
Address Array Read: Designates entry address and reads out the corresponding tag address
value/valid bit value.
Address Array Write: Designates entry address and writes the designated tag address value/valid
bit value.
9.3.2 Cache Data Array Read/Write Space
The cache data array has a compulsory read/write (figure 9.4).
31
10 9
21 0
Address
Upper 22 bits of the data array space address
(22 bits)
Entry address
–
(8 bits)
(2 bits)
31
0
Data
Data
(32 bits)
Figure 9.4 Cache Data Array
Data Array Read: Designates entry address and reads out the corresponding line of data.
Data Array Write: Designates entry address and writes designated data to the corresponding line.
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