SH7040 Datasheet, PDF (579/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 15.3 Analog Input Channel and ADDR Correspondence
Analog Input Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Note: * Except during buffer operation
A/D Data Register
ADDRA^*
ADDRB^*
ADDRC^*
ADDRD^*
ADDRE
ADDRF
ADDRG
ADDRH
15.2.2 A/D Control/Status Register (ADCSR)
The ADCSR is an 8-bit read/write register used for A/D conversion operation control and to
indicate status.
The ADCSR is initialized to H'00 by power-on reset or in standby mode. Manual reset does not
initialize ADCSR.
Bit: 7
6
5
4
3
ADF ADIE ADST CKS GRP
Initial value: 0
0
0
0
0
R/W: R/(W)^* R/W
R/W
R/W
R/W
Note: * The only value that can be written is a 0 to clear the flag.
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
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