SH7040 Datasheet, PDF (192/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

5. The RDRF flag of the SSR is set to 1 by each completion of a 1-byte data reception by the SCI,
an RxI interrupt is generated, and the DTC is activated. The received data is transferred from
RDR to RAM by the DTC, and the RDRF flag is 0 cleared.
6. After completion of 128 data transfers (DTCRA = 0), the DTER is cleared while the RDRF is
maintained as 1, and an RxI interrupt request is made to the CPU. The interrupt processing
routine clears the RDRF, and performs the other completion processing.
8.4 Cautions on Use
• DMAC and DTC register access by the DTC is prohibited.
• DTC register access by the DMAC is prohibited.
• When setting a bit in DTER, first ensure that all transfers on the DTC channel corresponding to
that DTER have ended, or disable the transfer source for each channel so that DTC transfer
corresponding to that DTER will not occur. The above restrictions do not apply for A mask
due to change in the access method of DTER. However, take caution when changing LSI to A
mask, since modification of the program is required.
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