SH7040 Datasheet, PDF (19/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
Page
Appendix C Pin
866
States
Table C.1 Pin
Modes During Reset,
Power-Down, and
Bus Right Release
Modes (144 Pin)
(cont)
Description
Table amended
Pin modes
Pin Function
Class Pin Name
Reset
Power-Down _{Bus Right}
Power-OnManual Standby Sleep Release
Standby in Bus
Right Release
MTU TIOC0A–TIOC0D, Z^*4
I/O
K^*1
I/O I/O
K^*1
TIOC1A–TIOC1D,
TIOC2A–TIOC2D,
TIOC3A, TIOC3C
TIOC3B,TIOC3D, Z^*4
I/O
Z
I/O I/O
Z
TIOC4A–TIOC4D
TCLKA–TCLKD Z^*4
I
Z
I
I
Z
Port
POE0–POE3
Z^*4
I
Z
I
I
Z
control
SCI
SCK0–SCK1
Z^*4
I/O
Z
I/O I/O
Z
TXD0–TCD1
Z^*4
O
O^*1
OO
O^*1
RXD0–RXD1
Z^*4
I
Z
I
I
Z
A/D
ADTRG
Z^*4
I
Z
I
I
Z
converter _AN0–AN7
Z
I
Z
I
I
Z
I/O Port PA0–PA23
Z^*4
I/O
K^*1
K I/O
K^*1
PB0–PB9
PC0–PC15
PD0–PD31
PE0–PE8,PE10
PE9,PE11–PE15 Z^*4
I/O
Z
K I/O
Z
PF0–PF17
Z
I
Z
I
I
Z
Notes: 1. There are instances where bus right release and transition to software standby mode
occur simultaneously due to the timing between BREQ and internal operations. In such
cases, standby mode results, but the standby state may be different.
The initial pin states depend on the mode. See section 18, Pin Function Controller
(PFC), for details.
2. I: Input, O: Output, H: High-level output, L: Low-level output, Z: High impedance,
K: Input pin with high impedance, output pin mode maintained.
*1 If the standby control register port high-impedance bits are set to 1, output pins become
high impedance.
*2 A21–A18 will become input ports after power-on reset.
*3 Input in the SH7044/SH7045 F-ZTAT version.
*4 General use I/O ports PAn, PBn, PCn, PDn, and PEn, as well as pins multiplexed with
them, are unstable during the RES setup time (t_RESS) immediately after the RES pin
goes to low level.