SH7040 Datasheet, PDF (163/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read
and/or write cycles.
Bit 3: RW1
0
1
Bit 2: RW0
0
1
0
1
Description
No user break interrupt occurs (initial value)
Break on read cycles
Break on write cycles
Break on both read and write cycles
• Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break
condition.
Bit 1: SZ1
Bit 0: SZ0
Description
0
0
Operand size is not a break condition (initial value)
1
Break on byte access
1
0
Break on word access
1
Break on longword access
Note:
When breaking on an instruction fetch, set the SZ0 bit to 0. All instructions are considered
to be word-size accesses (even when there are instructions in on-chip memory and 2
instruction fetches are done simultaneously in 1 bus cycle).
Operand size is word for instructions or determined by the operand size specified for the
CPU/DMAC data access. It is not determined by the bus width of the space being
accessed.
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