SH7040 Datasheet, PDF (30/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.7.7 Contention between TGR Write and Input Capture ............................................. 395
12.7.8 Contention between Buffer Register Write and Input Capture ............................ 396
12.7.9 Contention between TGR Write and Compare Match ......................................... 397
12.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 397
12.7.11 Counter Value during Complementary PWM Mode Stop ................................... 399
12.7.12 Buffer Operation Setting in Complementary PWM Mode................................... 399
12.7.13 Reset Sync PWM Mode Buffer Operation and Compare Match Flag ................. 400
12.7.14 Overflow Flags in Reset Sync PWM Mode ......................................................... 402
12.7.15 Notes on Compare Match Flags in Complementary PWM Mode ....................... 405
12.7.16 Contention between Overflow/Underflow and Counter Clearing ........................ 407
12.7.17 Contention between TCNT Write and Overflow/Underflow............................... 408
12.7.18 Cautions on Transition from Normal Operation or PWM Mode 1
to Reset-Synchronous PWM Mode ...................................................................... 409
12.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM
Mode..................................................................................................................... 409
12.7.20 Cautions on Using the Chopping Function in Complementary PWM Mode
or Reset Synchronous PWM Mode (A Mask Excluded)...................................... 409
12.7.21 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode
(A Mask Excluded)............................................................................................... 409
12.7.22 Cautions on Restarting with Sync Clear of Another Channel
in Complementary PWM Mode (A Mask Excluded)........................................... 410
12.8 MTU Output Pin Initialization........................................................................................... 411
12.8.1 Operating Modes .................................................................................................. 411
12.8.2 Reset Start Operation............................................................................................ 411
12.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. ................ 412
12.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error
during Operation, Etc............................................................................................ 412
12.9 Port Output Enable (POE) ................................................................................................. 443
12.9.1 Features................................................................................................................. 443
12.9.2 Block Diagram...................................................................................................... 444
12.9.3 Pin Configuration ................................................................................................. 445
12.9.4 Register Configuration.......................................................................................... 445
12.10 POE Register Descriptions ................................................................................................ 446
12.10.1 Input Level Control/Status Register (ICSR)......................................................... 446
12.10.2 Output Level Control/Status Register (OCSR)..................................................... 449
12.11 Operation ........................................................................................................................... 451
12.11.1 Input Level Detection Operation .......................................................................... 451
12.11.2 Output-Level Compare Operation ........................................................................ 452
12.11.3 Release from High-Impedance State .................................................................... 452
12.11.4 POE timing ........................................................................................................... 453
12.11.5 Usage Notes .......................................................................................................... 453
Section 13 Watchdog Timer (WDT) .............................................................................. 455
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