SH7040 Datasheet, PDF (457/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

(6) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Reset-Synchronous PWM Mode: Figure 12.101 shows an explanatory diagram of
the case where an error occurs in normal mode and operation is restarted in reset-synchronous
PWM mode after re-setting.
MTU output
1
2
3
RESET TMDR TOER
(normal) (1)
4
TIOR
(1 init
0 out)
5
PFC
(MTU)
6
TSTR
(1)
7
8
9
10
Match Error PFC TSTR
occurs (PORT) (0)
11
12
13
TIOR TIOR TOER
(0 init (disabled) (0)
0 out)
14
15
16
17
TOCR TMDR TOER PFC
(CPWM) (1) (MTU)
18
TSTR
(1)
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
PE9
High-Z
High-Z
PE11
High-Z
Figure 12.101 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous
PWM Mode
1 to 13 are the same as in figure 12.100.
14. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with
TOCR.
15. Set reset-synchronous PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU output with the PFC.
18. Operation is restarted by TSTR.
419