SH7040 Datasheet, PDF (85/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

2.1.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply
and accumulate registers store the results of multiply and accumulate operations. The procedure
register stores the return address from the subroutine procedure. The program counter stores
program addresses to control the flow of the processing. Figure 2.3 shows a system register.
31
MACH
MACL
0 _{Multiply and accumulate (MAC)}
registers high and low (MACH,
MACL): Stores the results of
multiply and accumulate operations.
31
PR
0 Procedure register (PR): Stores
a return address from a
subroutine procedure.
31
PC
0 _{Program counter (PC): Indicates}
the fourth byte (second instruction)
after the current instruction.
Figure 2.3 System Registers
2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset.
Table 2.1 Initial Values of Registers
Classification
General registers
Control registers
Register
R0–R14
R15 (SP)
SR
System registers
GBR
VBR
MACH, MACL, PR
PC
Initial Value
Undefined
Value of the stack pointer in the vector address table
Bits I3–I0 are 1111 (H'F), reserved bits are 0, and other
bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector address table
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