SH7040 Datasheet, PDF (213/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 3–0—CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle
extension specification is for making insertions to prevent extension of the RD signal or WRx
signal assert period beyond the length of the CSn signal assert period. Extended cycles insert
one cycle before and after each bus cycle, which simplifies interfaces with external devices and
also has the effect of extending write data hold time. Refer to section 10.3.3, CS Assert Period
Extension, for details.
SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert
extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access
and SW0 specifies the CS assert extension for CS0 space access.
Bit 3 (SW3)
0
1
Description
No CS3 space CS assert extension
CS3 space CS assert extension (initial value)
Bit 2 (SW2)
0
1
Description
No CS2 space CS assert extension
CS2 space CS assert extension (initial value)
Bit 1 (SW1)
0
1
Description
No CS1 space CS assert extension
CS1 space CS assert extension (initial value)
Bit 0 (SW0)
0
1
Description
No CS0 space CS assert extension
CS0 space CS assert extension (initial value)
10.2.3 Wait Control Register 1 (WCR1)
WCR1 is a 16-bit read/write register that specifies the number of wait cycles (0–15) for each CS
space.
WCR1 is initialized by power-on resets to H'FFFF, but is not initialized by manual resets or
software standbys.
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