SH7040 Datasheet, PDF (427/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.7 Notes and Precautions
This section describes contention and other matters requiring special attention during MTU
operations.
12.7.1 Input Clock Limitations
The input clock pulse width, in the case of single edge, must be 1.5 states or greater, and 2.5 states
or greater for both edges. Normal operation cannot be guaranteed with lesser pulse widths.
In phase counting mode, the phase difference between the two input clocks and the overlap must
be 1.5 states or greater for each, and the pulse width must be 2.5 states or greater. Input clock
conditions for phase counting mode are shown in figure 12.76.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
difference difference
Overlap
Overlap
Pulse width
Pulse width
Pulse width
Pulse width
Note: Phase difference and overlap: 1.5 states or greater
Pulse width: 2.5 states or greater
Figure 12.76 Phase Difference, Overlap, and Pulse Width in Phase Count Mode
12.7.2 Note on Cycle Setting
When setting a counter clearing by compare-match, clearing is done in the final state when TCNT
matches the TGR value (update timing for count value on TCNT match). The actual number of
states set in the counter is given by the following equation:
f
=
φ
(N +
1)
(f: counter frequency, φ: operating frequency, N: value set in the TGR)
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