SH7040 Datasheet, PDF (811/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

25.3.8 Serial Communication Interface Timing
Table 25.12 Serial Communication Interface Timing (Conditions: V_CC = 5.0 V ± 10%, AV_CC
= 5.0 V ± 10%, AV_CC = V_CC ± 10%, AV_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V, Ta
= – 20 to +75°C)
Item
Symbol Min
Input clock cycle
t _scyc
4
Input clock cycle (clock sync)
t _scyc
6
Input clock pulse width
t _sckw
0.4
Input clock rise time
t _sckr
—
Input clock fall time
t _sckf
—
Transmit data delay time (clock sync) t_TXD
—
Receive data setup time (clock sync) t_RXS
100
Receive data hold time (clock sync) t_RXH
100
Max
—
—
0.6
1.5
1.5
100
—
—
Unit
t _cyc
t _cyc
t _scyc
t _cyc
t _cyc
ns
ns
ns
Figure
25.27
25.28
SCK0, SCK1
t_sckw
t_sckr
t_sckf
t_scyc
Figure 25.27 Input Clock Timing
SCK0, SCK1
TXD0, TXD1
(Transmit data)
RXD0, RXD1
(Receive data)
t_scyc
t_TXD
t_RXS t_RXH
Figure 25.28 SCI I/O Timing (Clock Sync Mode)
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