SH7040 Datasheet, PDF (588/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

ADF
ADST
Set to 1 by software
Cleared to 0 by software
Channel 0
Channel 1
Conversion standby
A/D conversion 5
Conver-
A/D
A/D
sion ^Sampling conver- ^Sampling conver- ^Sampling
standby
1
sion 1
3
sion 3
5
Conversion
standby
Sampling
2
A/D
conver-
sion 2
Sampling
4
A/D
conver-
sion 4
Conversion
stopped
Channel 2 Conversion standby
Sampling 6
Channel 3 Conversion standby
ADDRA
ADDRB
Conver- Conver- Conver-
sion
sion
sion
result 1 result 2 result 3
Conver-
sion
result 4
ADDRC
ADDRD
Figure 15.5 A/D Converter Operation Example (Select-Scan Mode)
15.4.3 Group-Single Mode
Choose group-single mode when doing A/D conversions for multiple channels.
When the ADST bit is set to 1, A/D conversion is started according to the designated conversion
start conditions. The ADST bit is held to 1 during A/D conversion and is automatically cleared to
0 when all conversions for the designated input channels are completed.
The ADF flag is set to 1 when all conversions for the designated input channels are completed. If
the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared
by reading the ADCSR then writing a 0.
Figure 15.6 shows an example of operation in the group-single mode when AN0–AN2 are
selected.
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