SH7040 Datasheet, PDF (194/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

9.1.2 Block Diagram
Figure 9.2 shows a block diagram of the cache.
CCR
Cache tag
Cache
controller
Cache data
Cache
Bus state
controller
CCR: Cache control register
External bus
interface
Figure 9.2 Cache Block Diagram
9.1.3 Register Configuration
The cache has one register, which can be used to control the enabling or disabling of each cache
space. The register configuration is shown in table 9.1.
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