SH7040 Datasheet, PDF (456/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

(5) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Complementary PWM Mode: Figure 12.100 shows an explanatory diagram of the
case where an error occurs in normal mode and operation is restarted in complementary PWM
mode after re-setting.
MTU output
1
2
3
RESET TMDR TOER
(normal) (1)
4
TIOR
(1 init
0 out)
5
PFC
(MTU)
6
TSTR
(1)
7
8
9
10
Match Error PFC TSTR
occurs (PORT) (0)
11
12
13
TIOR TIOR TOER
(0 init (disabled) (0)
0 out)
14 15 (16) (17)
TOCR TMDR TOER PFC
(CPWM) (1) (MTU)
(18)
TSTR
(1)
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
PE9
High-Z
High-Z
PE11
High-Z
Figure 12.100 Error Occurrence in Normal Mode, Recovery in Complementary PWM
Mode
1 to 10 are the same as in figure 12.96.
11. Initialize the normal mode waveform generation section with TIOR.
12. Disable operation of the normal mode waveform generation section with TIOR.
13. Disable channel 3 and 4 output with TOER.
14. Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
15. Set complementary PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU output with the PFC.
18. Operation is restarted by TSTR.
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