SH7040 Datasheet, PDF (756/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

22.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
22.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase
block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the
error-protected state. (See table 22.8.)
Table 22.8 Hardware Protection
Function
Item
Description
Program Erase
FWP pin
protection
• When a high level is input to the FWP pin, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized, and the
Yes
Yes
program/erase-protected state is entered.
Reset/standby • In a reset (including a WDT overflow reset) and in
Yes
Yes
protection
standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are
initialized, and the program/erase-protected state is
entered.
• In a reset via the RES pin, the reset state is not entered
unless the RES pin is held low until oscillation stabilizes
after powering on. In the case of a reset during operation,
hold the RES pin low for the RES pulse width specified in
the AC Characteristics section.
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