SH7040 Datasheet, PDF (703/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section 20 64/128/256kB Mask ROM
20.1 Overview
This LSI is available with 64 kbytes, 128 kbytes, or 256 kbytes of on-chip ROM. The on-chip
ROM is connected to the CPU, direct memory access controller (DMAC) and data transfer
controller (DTC) through a 32-bit data bus (figures 20.1, 20.2, and 20.3). The CPU, DMAC, and
DTC can access the on-chip ROM in 8, 16, and 32-bit widths. Data in the on-chip ROM can
always be accessed in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0000FFFC
H'0000FFFD
H'0000FFFE
H'0000FFFF
Figure 20.1 Mask ROM Block Diagram (64-kbyte Version)
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