SH7040 Datasheet, PDF(201/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (201/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Section 10 Bus State Controller (BSC)

10.1 Overview

The bus state controller (BSC) divides up the address spaces and outputs control for various types

of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the LSI

without external circuitry.

10.1.1 Features

The BSC has the following features:

â¢ Address space is divided into five spaces

ï£§ A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum linear

4-Mbyte for on-chip ROM ineffective mode for address space CS0

ï£§ A maximum linear 4 Mbytes for each of the address spaces CS1âCS3

ï£§ A maximum linear 16 Mbytes for DRAM dedicated space

ï£§ Bus width can be selected for each space (8, 16, or 32 bits)

ï£§ Wait states can be inserted by software for each space

ï£§ Wait states can be inserted via the WAIT pin in external memory spce accesses.

ï£§ Outputs control signals for each space according to the type of memory connected

â¢ On-chip ROM and RAM interfaces

ï£§ On-chip RAM access of 32 bits in 1 state

ï£§ On-chip ROM access of 32 bits in 1 state

â¢ Direct interface to DRAM

ï£§ Multiplexes row/column addresses according to DRAM capacity

ï£§ Supports high-speed page mode and RAS down mode

â¢ Access control for each type of memory, peripheral LSI

ï£§ Address/data multiplex function

â¢ Refresh

ï£§ Supports CAS-before-RAS refresh (auto-refresh) and self-refresh

â¢ Refresh counter can be used as an interval timer

ï£§ Interrupt request generated upon compare match (CMI interrupt request signal)

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