SH7040 Datasheet, PDF (177/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Bit: 31 30 29 28 27 … 4
3
2
1
0
…
Initial value: *
*
*
*
*…*
*
*
*
*
R/W: — — — — — … — — — — —
Note: * Initial value is undefined.
8.2.4 DTC Initial Address Register (DTIAR)
The DTC initial address register (DTIAR) specifies the initial transfer source/transfer destination
address in repeat mode. In repeat mode, when the DTS bit is set to 1, specify the initial transfer
source address in the repeat area, and when the DTS bit is cleared to 0, specify the initial transfer
destination address in the repeat area.
The contents of this register are located in memory.
Bit: 31 30 29 28 27 … 4
3
2
1
0
…
Initial value: *
*
*
*
*…*
*
*
*
*
R/W: — — — — — … — — — — —
Note: * Initial value is undefined.
8.2.5 DTC Transfer Count Register A (DTCRA)
DTCRA is a 16-bit register that specifies the number of DTC transfers. The contents of this
register are located in memory.
In normal mode it functions as a 16-bit transfer counter. The number of transfers is 1 when the set
value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000.
In repeat mode, DTCRAH maintains the transfer count and DTCRAL functions as an 8-bit
transfer counter. The number of transfers is 1 when the set value is DTCRAH = DTCRAL = H'01,
255 when they are H'FF, and 256 when it is H'00.
In block transfer mode it functions as a 16-bit transfer counter. The number of transfers is 1 when
the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000.
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