82801CA Datasheet, PDF (98/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.5.5 DMA Byte Enable Generation
The byte enables generated by the ICH3 on I/O reads and writes must correspond to the size of the
I/O device. Table 5-12 defines the byte enables asserted for 8- and 16-bit DMA cycles.
Table 5-12. DMA I/O Cycle Width vs. BE[3:0]#
BE[3:0]#
1110b
1100b
Description
8-bit DMA I/O Cycle: Channels 0–3
16-bit DMA I/O Cycle: Channels 5–7
NOTE: For verify cycles the value of the Byte Enables (BEs) is a “don’t care”.
5.5.6
DMA Cycle Termination
DMA cycles are terminated when a terminal count is reached in the DMA controller and the
channel is not in autoinitialize mode, or when the PC/PCI device deasserts its request. The PC/PCI
device must follow explicit rules when deasserting its request, or the ICH3 may not see it in time
and run an extra I/O and memory cycle.
The PC/PCI device must deassert its request 7 PCICLKs before it generates TRDY# on the I/O
read or write cycle, or the ICH3 is allowed to generate another DMA cycle. For transfers to
memory, this means that the memory portion of the cycle will be run without an asserted PC/PCI
REQ#.
5.5.7
LPC DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special
encodings on LAD[3:0] from the host. Single, demand, verify, and increment modes are supported
on the LPC interface. Channels 0–3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel
4 is reserved as a generic bus master request.
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Intel^® 82801CA ICH3-S Datasheet