82801CA Datasheet, PDF (140/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.6 Dynamic Processor Clock Control
The ICH3 has extensive control for dynamically starting and stopping system clocks. The clock
control is used for transitions among the various S0/Cx states, and processor throttling. Each
dynamic clock control method is described in this section. The various Sleep states may also
perform types of non-dynamic clock control.
The ICH3 supports the ACPI C0, C1 and C2 states. The Dynamic processor Clock control is
handled using the following signals:
• STPCLK#:Used to halt processor instruction stream.
The C1 state is entered based on the processor performing an auto halt instruction.
The C2 state is entered based on the processor reading the Level 2 Register in the ICH3.
A C1, C2 state ends due to a Break event. Based on the break event, the ICH3 returns the system to
C0 state. Table 5-39 lists the possible break events from C2. The break events from C1 are
indicated in the processor’s datasheet
.
Table 5-39. Break Events
Event
Any unmasked interrupt goes
active
Any internal event that will
cause an NMI or SMI#
Any internal event that will
cause INIT# to go active
Processor Pending Break
Event Indication
Breaks from
C2
Comment
IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC.
Since SCI is an interrupt, any SCI will also be a break
event.
C2
Many possible sources
C2
Could be indicated by the keyboard controller via the
RCIN input signal.
C2
Only available if FERR# enabled for break event
indication (See FERR# Mux-En in Section 9.1.22)
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Intel^® 82801CA ICH3-S Datasheet