82801CA Datasheet, PDF (351/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.16
BUS_ADDR_TRACK— Bus Address Tracker Register
I/O Address:
Lockable:
Power Well:
PMBASE +4Ch
No
Core
Attribute:
Size:
Usage:
RO
16-bit
Legacy Only
This register could be used by the SMI# handler to assist in determining what was the last cycle
from the processor. BUS_ADDR_TRACK may not contain “expected” last I/O cycle data if
Asynchronous SMIs and Synchronous SMIs are occurring simultaneously. This register only
reports “expected” last I/O cycle data if Asynchronous SMIs are disabled.
9.8.3.17
Bit
Description
Corresponds to the low 16 bits of the last I/O cycle, as would be defined by the PCI AD[15:0] signals
15:0 on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI#
active. This functionality is useful for figuring out which I/O was last being accessed.
BUS_CYC_TRACK— Bus Cycle Tracker Register
I/O Address:
Lockable:
Power Well:
PMBASE +4Eh
No
Core
Attribute:
Size:
Usage:
RO
8-bit
Legacy Only
This register could be used by the SMM handler to assist in determining what was the last cycle
from the processor. BUS_CYC_TRACK may not contain “expected” last I/O cycle data if
Asynchronous SMIs and Synchronous SMIs are occurring simultaneously. This register only
reports “expected” last I/O cycle data if Asynchronous SMIs are disabled.
Bit
Description
7:4
Corresponds to the byte enables, as would be defined by the PCI C/BE# signals on the PCI bus
(even though it may not be a real PCI cycle). The value is latched based on SMI# going active.
3:0
Corresponds to the cycle type, as would be defined by the PCI C/BE# signals on the PCI bus (even
though it may not be a real PCI cycle). The value is latched based on SMI# going active.
Intel^® 82801CA ICH3-S Datasheet
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