82801CA Datasheet, PDF (347/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.12
SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 34h
0000h
No
Core
Attribute:
Size:
Usage:
R/W
32-bit
ACPI or Legacy
Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH3 will cause an SMI# (except
bits 8–10 and 12, which do not need enable bits since they are logic ORs of other registers that have
enable bits).
Bit
Description
31:17 Reserved.
SMBus SMI Status (SMBUS_SMI_STS)—R/WC.
0 = This bit is cleared by writing a 1 to its bit position. This bit is set from the 64 kHz clock domain
used by the SMBus. Software must wait at least 15.63 µs after the initial assertion of this bit
before clearing it.
1 = Indicates that the SMI# was caused by:
16
• The SMBus Slave receiving a message, or
• The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS
bit is cleared, or
• The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and the
SMB_SMI_EN bits are set, or
• The ICH3 detecting the SMLINK_SLAVE_SMI command while in the S0 state.
SERIRQ_SMI_STS—RO.
15 _{0 = SMI# was not caused by SERIRQ decoder. This is not a sticky bit.}
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
PERIODIC_STS—R/WC.
14 ^{0 = This bit is cleared by writing a 1 to its bit position.}
1 = This bit will be set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is
also set, the ICH3 will generate an SMI#.
TCO_STS—RO.
13 _{0 = SMI# not caused by TCO logic.}
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event.
Device Monitor Status (DEVMON_STS)—RO.
0 = SMI# not caused by Device Monitor.
12 ^{1 = Set under any of the following conditions:}
- Any of the DEV[7:4]_TRAP_STS bits are set and the corresponding DEV[7:4]_TRAP_EN bits
are also set.
- Any of the DEVTRAP_STS bits are set and the corresponding DEVTRAP_EN bits are also set.
Microcontroller SMI# Status (MCSMI_STS)—R/WC.
0 = Indicates that there has been no access to the power management microcontroller range (62h or
11
66h). This bit is cleared by software writing a 1 to the bit position.
1 = Set if there has been an access to the power management microcontroller range (62h or 66h). If
this bit is set, and the MCSMI_EN bit is also set, the ICH3 will generate an SMI#.
GPE1_STS—RO. This bit is a logical OR of the bits in the GPE1_STS register that are also set up to
cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the
GPE1_EN register. Bits that are not routed to cause an SMI# will have no effect on the GPE1_STS
10 _bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
GPE0_STS—RO. This bit is a logical OR of the bits in the GPE0_STS register that also have the
corresponding bit set in the GPE0_EN register.
9
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
Intel^® 82801CA ICH3-S Datasheet
347