82801CA Datasheet, PDF (23/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Tables
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Industry Specifications ...................................................................................29
PCI Devices and Functions............................................................................31
Hub Interface Signals.....................................................................................39
LAN Connect Interface Signals......................................................................39
EEPROM Interface Signals............................................................................39
Firmware Hub Interface Signals.....................................................................40
PCI Interface Signals .....................................................................................40
IDE Interface Signals .....................................................................................43
LPC Interface Signals ....................................................................................44
Interrupt Signals.............................................................................................44
USB Interface Signals....................................................................................45
Power Management Interface Signals ...........................................................45
Processor Interface Signals ...........................................................................46
SM Bus Interface Signals...............................................................................48
System Management Interface Signals .........................................................48
Real Time Clock Interface..............................................................................48
Other Clocks ..................................................................................................49
Miscellaneous Signals ...................................................................................49
AC ’97 Link Signals........................................................................................49
General Purpose I/O Signals .........................................................................50
Power and Ground Signals ............................................................................51
Functional Strap Definitions ...........................................................................52
Test Mode Selection ......................................................................................54
Intel^® ICH3 Power Planes..............................................................................55
Integrated Pull-Up and Pull-Down Resistors..................................................56
IDE Series Termination Resistors..................................................................56
Power Plane and States for Output and I/O Signal........................................57
Power Plane for Input Signals........................................................................60
Intel^® ICH3 and System Clock Domains........................................................63
Type 0 Configuration Cycle Device Number Translation ...............................69
LPC Cycle Types Supported..........................................................................86
Start Field Bit Definitions................................................................................86
Cycle Type Bit Definitions ..............................................................................87
Transfer Size Bit Definition ............................................................................87
SYNC Bit Definition........................................................................................88
Intel^® ICH3 Response to Sync Failures .........................................................88
DMA Transfer Size.........................................................................................93
Address Shifting in 16-Bit I/O DMA Transfers................................................93
DMA Cycle vs. I/O Address ...........................................................................97
PCI Data Bus vs. DMA I/O port size ..............................................................97
DMA I/O Cycle Width vs. BE[3:0]#.................................................................98
Counter Operating Modes............................................................................104
Interrupt Controller Core Connections .........................................................106
Interrupt Status Registers ............................................................................107
Content of Interrupt Vector Byte ..................................................................107
APIC Interrupt Mapping ...............................................................................114
Arbitration Cycles.........................................................................................115
APIC Message Formats...............................................................................116
EOI Message ...............................................................................................116
Intel^® 82801CA ICH3-S Datasheet
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