82801CA Datasheet, PDF (272/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.29
8.1.30
PCI_MAST_STS—PCI Master Status Register
(HUB-PCI—D30:F0)
Offset Address: 82h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
Internal PCI Master Request Status (INT_MREQ_STS)—R/WC.
7
0 = Software clears this bit by writing a 1 to the bit position.
1 = The ICH3’s internal DMA controller or LPC has requested use of the PCI bus.
Internal LAN Master Request Status (LAN_MREQ_STS)—R/WC.
6
0 = Software clears this bit by writing a 1 to the bit position.
1 = The ICH3’s internal LAN controller has requested use of the PCI bus.
PCI Master Request Status (PCI_MREQ_STS)—R/WC. Allows software to see if a particular bus
master has requested use of the PCI bus. For example, bit 0 will be set if ICH3 has detected
5:0 ^{REQ[0]# asserted and bit 5 will be set if ICH3 detected REQ[5]# asserted.}
0 = Software clears these bits by writing a 1 to the bit position.
1 = The associated PCI master has requested use of the PCI bus.
ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Offset Address: 90h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
This register configures the ICH3’s Device 30 responses to various system errors. The actual
assertion of the internal SERR# (routed to cause NMI# or SMI#) is enabled via the PCI Command
register.
Bit
Description
7:3 Reserved.
SERR# Enable on Receiving Target Abort (SERR_RTA_EN)—R/W.
2 _{0 = Disable}
1 = Enable. When SERR_EN is set, the ICH3 will report SERR# when SERR_RTA is set.
SERR# Enable on Delayed Transaction Timeout (SERR_DTT_EN)—R/W.
1 _{0 = Disable}
1 = Enable. When SERR_EN is set, the ICH3 will report SERR# when SERR_DTT is set.
0 Reserved.
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Intel^® 82801CA ICH3-S Datasheet