82801CA Datasheet, PDF (9/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

5.12.8.4 Processor Initiated Passive Cooling
(Via Programmed Duty Cycle on STPCLK#)...................147
5.12.8.5 Active Cooling..................................................................147
5.12.9 Event Input Signals and Their Usage .............................................147
5.12.9.1 PWRBTN#–Power Button ...............................................147
5.12.9.2 RI#—Ring Indicate ..........................................................148
5.12.9.3 PME#—PCI Power Management Event..........................148
5.12.10 ALT Access Mode...........................................................................148
5.12.10.1 Write Only Registers with Read Paths in ALT
Access Mode ...................................................................149
5.12.10.2 PIC Reserved Bits ...........................................................151
5.12.10.3 Read Only Registers with Write Paths in ALT
Access Mode ...................................................................151
5.12.11 System Power Supplies, Planes, and Signals ................................152
5.12.11.1 Power Plane Control with SLP_S3# and SLP_S5#.........152
5.12.11.2 PWROK Signal ................................................................152
5.12.11.3 VRMPWRGD Signal........................................................152
5.12.11.4 Controlling Leakage and Power Consumption
During Low-Power States................................................152
5.12.12 Clock Generators ............................................................................153
5.12.13 Legacy Power Management Theory of Operation ..........................153
5.12.13.1 APM Power Management................................................153
5.13 System Management (D31:F0)....................................................................154
5.13.1 Theory of Operation ........................................................................154
5.13.1.1 Detecting a System Lockup.............................................154
5.13.1.2 Handling an Intruder ........................................................154
5.13.1.3 Detecting Improper FWH Programming ..........................155
5.13.1.4 Handling an ECC Error or Other Memory Error...............155
5.13.2 Alert on LAN* ..................................................................................155
5.14 General Purpose I/O ....................................................................................159
5.14.1 GPIO Mapping ................................................................................159
5.14.2 Power Wells ....................................................................................161
5.14.3 SMI# and SCI Routing ....................................................................161
5.14.4 Power Wells ....................................................................................161
5.15 IDE Controller (D31:F1) ...............................................................................161
5.15.1 PIO Transfers..................................................................................162
5.15.1.1 IDE Port Decode..............................................................162
5.15.1.2 IDE Legacy Mode and Native Mode................................162
5.15.1.3 PIO IDE Timing Modes....................................................163
5.15.1.4 IORDY Masking...............................................................164
5.15.1.5 PIO 32-Bit IDE Data Port Accesses ................................164
5.15.1.6 PIO IDE Data Port Prefetching and Posting ....................164
5.15.2 Bus Master Function .......................................................................165
5.15.2.1 Physical Region Descriptor Format .................................165
5.15.2.2 Bus Master IDE Timings..................................................166
5.15.2.3 Interrupts .........................................................................166
5.15.2.4 Bus Master IDE Operation...............................................167
5.15.2.5 Error Conditions...............................................................168
5.15.2.6 Intel^® 8237-Like Protocol.................................................168
5.15.3 Ultra ATA/33 Protocol .....................................................................169
5.15.3.1 Signal Descriptions..........................................................169
5.15.3.2 Operation.........................................................................170
5.15.3.3 CRC Calculation ..............................................................170
5.15.4 Ultra ATA/66 Protocol .....................................................................171
Intel^® 82801CA ICH3-S Datasheet
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