82801CA Datasheet, PDF (386/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

USB 1.1 Controllers Registers
11.1.14
INTR_PN—Interrupt Pin Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
3Dh
Function 0: 01h
Function 1: 02h
Function 2: 03h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Reserved.
Interrupt Pin (INT_PN). The values of 01h, 02h, and 03h in function 0, 1, and 2, respectively, indicate
to software that the corresponding ICH3 USB controllers drive the INTA#, INTB#, and INTC# PCI
signals. Read-Only.
2:0
Note that this does not determine the mapping to the ICH3 PIRQ inputs. Function 0 drives PIRQA;
Function 1 drives PIRQD; Function 2 drives PIRQC. Function 1 does not use the corresponding
mapping in order to spread the interrupts with AC ’97, which has historically been mapped to PIRQB.
11.1.15
SB_RELNUM—Serial Bus Release Number Register
(USB—D29:F0/F1/F2)
Address Offset:
60h
Default Value:
10h
Attribute:
Size:
RO
8 bits
Bit
Description
Serial Bus Release Number—RO.
7:0
10h = Indicates that the USB controller is compliant with the USB specification release 1.0.
11.1.16
USB_LEGKEY—USB Legacy Keyboard/Mouse Control
Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
C0–C1h
2000h
Attribute:
Size:
R/W
16 bits
This register is implemented separately in each of the USB 1.1 functions. However, the enable and
status bits for the trapping logic are OR’ed and shared, respectively, since their functionality is not
specific to any one host controller.
Bit
Description
SMI Caused by End of Pass-through (SMIBYENDPS)—R/WC. Indicates if the event occurred.
Note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. It is up
15 ^{to the SMM code to use the enable bit to determine the exact cause of the SMI#.}
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
14 Reserved.
PCI Interrupt Enable (USBPIRQEN)—R/W. Used to prevent the USB controller from generating an
interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to
13 generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software.
0 = Disable.
1 = Enable.
386
Intel^® 82801CA ICH3-S Datasheet