82801CA Datasheet, PDF (119/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Lowest Priority without Focus Processor (FP) Message
This message format is used to deliver an interrupt in the lowest priority mode in which it does not
have a Focus Process. Cycles 1 through 21 for this message is same as for the short message
discussed above. Status cycle 19 identifies if there is a Focus processor (10) and a status value of 11
in cycle 20 indicates the need for lowest priority arbitration.
Table 5-23. Lowest Priority Message (Without Focus Processor)
Cycle
1
2–5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Bit 1
1
ARBID
NOT(DM)
NOT(M1)
NOT(L)
NOT(V7)
NOT(V5)
NOT(V3)
NOT(V1)
NOT(D7)
NOT(D5)
NOT(D3)
NOT(D1)
NOT(C1)
1
NOT(A)
NOT(A1)
P7
P6
P5
P4
P3
P2
P1
P0
ArbID3
ArbID2
ArbID1
ArbID0
S
1
Bit 0
0
1
NOT(M2)
NOT(M0)
NOT(TM)
NOT(V6)
NOT(V4)
NOT(V2)
NOT(V0)
NOT(D6)
NOT(D4)
NOT(D2)
NOT(D0)
NOT(C0)
1
NOT(A)
NOT(A1)
1
1
1
1
1
1
1
1
1
1
1
1
S
1
Comments
Normal Arbitration
Arbitration ID
DM = Destination Mode from bit 11 of the redirection table register
M2-M0 = Delivery Mode from bits 10:8 of the redirection table
register
L = Level, TM = Trigger Mode
Interrupt vector bits V7–V0 from redirection table register
Destination field from bits 63:56 of redirection table register
Checksum for Cycles 6–16
Postamble
Status Cycle 0.
Status Cycle 1.
Inverted Processor Priority P7–P0
Status
Idle
NOTES:
1. Cycle 21 through 28 are used to arbitrate for the lowest priority processor. The processor that takes part in
the arbitration drives the processor priority on the bus. Only the local APICs that have “free interrupt slots” will
participate in the lowest priority arbitration.
2. Cycles 29 through 32 are used to break tie in case two more processors have lowest priority. The bus
arbitration ID's are used to break the tie.
Intel^® 82801CA ICH3-S Datasheet
119