82801CA Datasheet, PDF (215/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
ICH3 core well outputs may be used as strapping options for the ICH3, sampled during system
reset. These signals may have weak pullups/pulldowns on them, however this will not interfere
with link operation. ICH3 inputs integrate weak pulldowns to prevent floating traces when a
secondary codec is not attached. When the shut off bit in the control register is set, all buffers will
be turned off and the pins will be held in a steady state, based on these pullups/pulldowns.
BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary
clocking to support the twelve, 20-bit time slots. AC-link serial data is transitioned on each rising
edge of BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of
BIT_CLK.
Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via the
AC_SYNC signal, as shown in Figure 5-21. The primary codec drives the serial bit clock onto the
AC-link, which the AC ’97 controller then qualifies with the AC_SYNC signal to construct data
frames. AC_SYNC, fixed at 48 kHz, is derived by dividing down BIT_CLK. AC_SYNC remains
high for a total duration of 16 BIT_CLKs at the beginning of each frame. The portion of the frame
where AC_SYNC is high is defined as the tag phase. The remainder of the frame where AC_SYNC
is low is defined as the data phase. Each data bit is sampled on the falling edge of BIT_CLK.
Figure 5-21. AC-Link Protocol
SYNC
BIT_CLK
SDIN
Tag Phase
12.288 MHz
81.4 nS
Data Phase
20.8uS
(48 KHz)
Codec
Ready
slot(1) slot(2)
slot(12) "0" "0" "0" 19
0
19
0 19
0
19
0
End of previous
Audio Frame
Time Slot "Valid"
Bits
("1" = time slot contains valid PCM
data)
Slot 1
Slot 2
Slot 3
Slot 12
AC_Link_Protocol
The ICH3 has two SDIN pins allowing a single or dual codec configuration. When two codecs are
connected, the primary and secondary codecs can be connected to either SDIN line, however it is
recommended that the primary codec be attached to SDIN [0]. The ICH3 does not distinguish
between primary and secondary codecs on its SDIN[1:0] pins, however the registers do distinguish
between SDIN[0] and SDIN[1] for wake events, etc. The primary codec can be an AC (audio
codec), MC (modem codec), or AMC (audio/modem codec) device. The secondary codec can be
an AC, MC, or AMC device.
The MC can be either on the primary or the secondary codec, while the AC can be either on the
primary or the secondary codec, or BOTH the primary or the secondary codec.
The ICH3 does not support optional test modes as outlined in the Audio Codec ’97, Revision 2.2
specification.
Intel^® 82801CA ICH3-S Datasheet
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