82801CA Datasheet, PDF (147/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.8.4
5.12.8.5
Processor Initiated Passive Cooling (Via Programmed Duty Cycle on
STPCLK#)
Using the THTL_EN and THTL_DTY bits, the ICH3 can force a programmed duty cycle on the
STPCLK# signal. This will reduce the effective instruction rate of the processor and cut its power
consumption and heat generation.
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH3 can be used to turn on/off a fan.
5.12.9
Event Input Signals and Their Usage
The ICH3 has various input signals that trigger specific events. This section describes those signals
and how they should be used.
5.12.9.1 PWRBTN#–Power Button
The ICH3 PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition
descriptions are included in the following table. Note that the transitions start as soon as the
PWRBTN# is pressed (but after the de-bounce logic), and does not depend on when the Power
Button is released.
Table 5-44. Transitions Due to Power Button
Present
State
Event
Transition/Action
S0/Cx PWRBTN# goes low
S1–S5 PWRBTN# goes low
SMI# or SCI generated
(depending on SCI_EN)
Wake Event. Transitions to
S0 state.
G3
PWRBTN# pressed
None
S0–S4
PWRBTN# held low for
at least 4 consecutive
seconds
Unconditional transition to S5
state.
Comment
Software will typically initiate
a Sleep state.
Standard wakeup
No effect since no power.
Not latched nor detected.
No dependence on processor
(such as Stop-Grant cycles) or
any other subsystem.
Power Button Override Function
If PWRBTN# is observed active for at least 4 consecutive seconds, then the state machine should
unconditionally transition to the G2/S5 state, regardless of present state (S0–S4). In this case, the
transition to the G2/S5 state should not depend on any particular response from the processor
(e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.
Note:
The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
4-second timer starts counting when the ICH3 is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1–S5), the assertion will cause a wake
event. Once the system has resumed to the S0 state, the 4-second timer will start.
Intel^® 82801CA ICH3-S Datasheet
147