82801CA Datasheet, PDF (422/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
Table 13-3. Native Audio Bus Master Control Registers
Offset
00h
04h
05h
06h
08h
0Ah
0Bh
10h
14h
15h
16h
18h
1Ah
1Bh
20h
24h
25h
26h
28h
2Ah
2Bh
2Ch
30h
34h
Mnemonic
Name
PI_BDBAR
PI_CIV
PI_LVI
PCM In Buffer Descriptor list Base Address Register
PCM In Current Index Value
PCM In Last Valid Index
PI_SR
PCM In Status Register
PI_PICB PCM In Position In Current Buffer
PI_PIV
PCM In Prefetched Index Value
PI_CR
PCM In Control Register
PO_BDBAR PCM Out Buffer Descriptor list Base Address Register
PO_CIV
PO_LVI
PO_SR
PCM Out Current Index Value
PCM Out Last Valid Index
PCM Out Status Register
PO_PICB PCM Out Position In Current Buffer
PO_PIV PCM Out Prefetched Index Value
PO_CR PCM Out Control Register
MC_BDBAR Mic. In Buffer Descriptor list Base Address Register
PM_CIV Mic. In Current Index Value
MC_LVI
MC_SR
MC_PICB
Mic. In Last Valid Index
Mic. In Status Register
Mic In Position In Current Buffer
MC_PIV Mic. In Prefetched Index Value
MC_CR Mic. In Control Register
GLOB_CNT Global Control
GLOB_STA Global Status
ACC_SEMA Codec Write Semaphore Register
Default
00000000h
00h
00h
0001h
0000h
00h
00h
00000000h
00h
00h
0001h
0000h
00h
00h
00000000h
00h
00h
0001h
0000h
00h
00h
00000000h
00000000h
00h
Access
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
RO
R/W
13.2.1
x_BDBAR—Buffer Descriptor Base Address Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
00000000h
Size:
No
Power Well:
R/W
32 bits
Core
Bit
Description
Buffer Descriptor Base Address[31:3]—R/W. These bits represent address bits 31:3. The data
31:3 should be aligned on 8-byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
2:0 Hardwired to 0.
422
Intel^® 82801CA ICH3-S Datasheet