82801CA Datasheet, PDF (52/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
2.20 Pin Straps
2.20.1 Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of
PWROK to select configurations, and then revert later to their normal usage. To invoke the
associated mode, the signal should be driven at least 4 PCI clocks prior to the time it is sampled.
Table 2-20. Functional Strap Definitions
Signal
Usage
When Sampled
Comment
AC_SDOUT Safe Mode
EE_DOUT Reserved
Rising Edge of
PWROK
GNT[A]#
Top-Swap Override
Rising Edge of
PWROK
DPSLPVR
Hub Interface
Termination
Scheme (Normal vs.
Enhanced)
Rising Edge of
PWROK
HICOMP
Hub Interface
Scheme (HI 1.5)
Rising Edge of
PWROK
SPKR
No Reboot
Rising Edge of
PWROK
The signal has a weak internal pull-down. If the
signal is sampled high, the ICH3 will set the
processor speed strap pins for safe mode. Refer to
processor specification for speed strapping
definition. The status of this strap is readable via the
SAFE_MODE bit (bit 2, D31: F0, Offset D4h).
System designers should include a placeholder for
a pull-down resistor on EE_DOUT but do not
populate the resistor.
The signal has a weak internal pull-up. If the signal
is sampled low, this indicates that the system is
strapped to the “Top-Swap” mode (ICH3 will invert
A16 for all cycles targeting FWH BIOS space). The
status of this strap is readable via the Top-Swap bit
(bit 13, D31: F0, Offset D4h). Note that software will
not be able to clear the Top-Swap bit until the
system is rebooted without GNT[A]# being pulled
down.
Low (default)–Hub Interface 1.0 series or Hub
Interface 1.5 parallel termination
High (external pull-up to Vcc1_8)–Not supported in
ICH3.
External pull-up to Vcc1_8.
NOTE: See the platform design guide for resistor
values and routing guidelines for each hub
interface mode.
The signal has a weak internal pull-down. If the
signal is sampled high, this indicates that the
system is strapped to the “No Reboot” mode (ICH3
will disable the TCO Timer system reboot feature).
The status of this strap is readable via the
NO_REBOOT bit (bit 1, D31: F0, Offset D4h).
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Intel^® 82801CA ICH3-S Datasheet