82801CA Datasheet, PDF (24/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

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Short Message............................................................................................. 117
APIC Bus Status Cycle Definition ................................................................ 118
Lowest Priority Message (Without Focus Processor) .................................. 119
Remote Read Message ............................................................................... 120
Interrupt Message Address Format ............................................................. 123
Interrupt Message Data Format................................................................... 123
Stop Frame Explanation .............................................................................. 125
Data Frame Format ..................................................................................... 126
Configuration Bits Reset by RTCRST# Assertion........................................ 129
INIT# Going Active....................................................................................... 131
NMI Sources ................................................................................................ 132
DP Signal Differences.................................................................................. 132
Frequency Strap Behavior Based on Exit State .......................................... 133
Frequency Strap Bit Mapping ...................................................................... 133
General Power States for Systems using Intel^® ICH3 ................................. 135
State Transition Rules for Intel^® ICH3 ......................................................... 136
System Power Plane ................................................................................... 137
Causes of SMI# and SCI ............................................................................. 138
Break Events ............................................................................................... 140
Sleep Types................................................................................................. 143
Causes of Wake Events .............................................................................. 144
GPI Wake Events ........................................................................................ 144
Transitions Due to Power Failure ................................................................ 145
Transitions Due to Power Button ................................................................. 147
Transitions Due to RI# Signal ...................................................................... 148
Write Only Registers with Read Paths in ALT Access Mode....................... 149
PIC Reserved Bits Return Values................................................................ 151
Register Write Accesses in ALT Access Mode............................................ 151
Intel^® ICH3 Clock Inputs .............................................................................. 153
Alert on LAN* Message Data....................................................................... 158
GPIO(s) Mapping......................................................................................... 159
IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select) ..... 163
IDE Legacy I/O Ports: Control Block Registers (CS3x# Chip Select) .......... 163
IDE Transaction Timings (PCI Clocks) ........................................................ 164
Interrupt/Active Bit Interaction Definition...................................................... 168
UltraATA/33 Control Signal Redefinitions.................................................... 169
Frame List Pointer Bit Description ............................................................... 172
TD Link Pointer ............................................................................................ 173
TD Control and Status ................................................................................. 174
TD Token ..................................................................................................... 176
TD Buffer Pointer ......................................................................................... 176
Queue Head Block....................................................................................... 177
Queue Head Link Pointer ............................................................................ 177
Queue Element Link Pointer........................................................................ 177
Command Register, Status Register and TD Status Bit Interaction ............ 180
Queue Advance Criteria .............................................................................. 182
USB Schedule List Traversal Decision Table .............................................. 183
PID Format .................................................................................................. 185
PID Types .................................................................................................... 185
Address Field............................................................................................... 186
Endpoint Field.............................................................................................. 186
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Intel^® 82801CA ICH3-S Datasheet