82801CA Datasheet, PDF (66/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Note:
If the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the ICH3 will not
allow upstream requests to be performed until the cycle completion. This may be critical for
isochronous buses which assume certain timing for their data flow, such as AC ’97 or USB.
Devices on these buses may suffer from underrun if the asynchronous traffic is too heavy.
Underrun means that the same data is sent over the bus while ICH3 is not able to issue a request for
the next data. Snoop cycles are not permitted while the Processor System Bus is locked.
Note:
Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a short
duration (a few microseconds at most). If a system has a very large number of locked cycles and
some that are very long, then the system will definitely experience underruns and overruns. The
units most likely to have problems are the AC '97 controller and the USB controllers. Other units
could get underruns/overruns, but are much less likely. The IDE controller (due to its stalling
capability on the cable) should not get any underruns or overruns.
5.1.2
PCI-to-PCI Bridge Model
From a software perspective, the ICH3 contains a PCI-to-PCI bridge. This bridge connects the hub
interface to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH3 can have its
decode ranges programmed by existing plug-and-play software such that PCI ranges do not
conflict with AGP and graphics aperture ranges in the Host controller.
5.1.3
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots) the ICH3 will assert one
address signal as an IDSEL. When accessing device 0, the ICH3 will assert AD16. When accessing
Device 1, the ICH3 will assert AD17. This mapping continues all the way up to device 15 where
the ICH3 asserts AD31. Note that the ICH3’s internal functions (AC ’97, IDE, USB, and PCI
Bridge) are enumerated like they are on a separate PCI bus (the hub interface) from the external
PCI bus. The integrated LAN Controller is Device 8 on the ICH3’s PCI bus, and hence it uses
AD24 for IDSEL
5.1.4
SERR# Functionality
There are several internal and external sources that can cause SERR#. The ICH3 can be
programmed to cause an NMI based on detecting that an SERR# condition has occurred. The NMI
can also be routed to instead cause an SMI#. Note that the ICH3 does not drive the external PCI bus
SERR# signal active onto the PCI bus. The external SERR# signal is an input into the ICH3 driven
only by external PCI devices. The conceptual logic diagrams in Figure 5-1 and Figure 5-2 illustrate
all sources of SERR#, along with their respective enable and status bits. Figure 5-3 shows how the
ICH3 error reporting logic is configured for NMI# generation.
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Intel^® 82801CA ICH3-S Datasheet