82801CA Datasheet, PDF (167/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.15.2.4
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are
required:
1. Software prepares a PRD Table in system memory. The PRD Table must be dword aligned and
must not cross a 64-Kbyte boundary.
2. Software provides the starting address of the PRD Table by loading the PRD table pointer
register. The direction of the data transfer is specified by setting the read/write control bit. The
interrupt bit and error bit in the status register are cleared.
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a '1' to the start bit in the command
register. The first entry in the PRD table is fetched and loaded into two registers which are not
visible by software, the current base and current count registers. These registers hold the
current value of the address and byte count loaded from the PRD table. The value in these
registers is only valid when there is an active command to an IDE device.
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the IDE
device. The IDE device and the host controller may or may not throttle the transfer several
times. When the last data transfer for a region has been completed on the IDE interface, the
next descriptor is fetched from the table. The descriptor contents are loaded into the current
base and current count registers.
7. At the end of the transfer the IDE device signals an interrupt.
8. In response to the interrupt, software resets the start/stop bit in the command register. It then
reads the controller status followed by the drive status to determine if the transfer completed
successfully.
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers
terminate when the physical region described by the last PRD in the table has been completely
transferred. The active bit in the status register will be reset and the DDRQ signal will be masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state) when a
terminal count condition exists; that is, the current region descriptor has the EOL bit set and that
region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when
the interrupt bit in the Bus Master IDE Status Register is set. Software that reads the status register
and finds the error bit reset, and either the active bit reset or the interrupt bit set, can be assured that
all data destined for system memory has been transferred and that data is valid in system memory.
Table 5-55 describes how to interpret the interrupt and active bits in the status register after a DMA
transfer has started.
During concurrent DMA or Ultra ATA transfers, the ICH3 IDE interface will arbitrate between the
primary and secondary IDE cables when a PRD expires.
Intel^® 82801CA ICH3-S Datasheet
167