82801CA Datasheet, PDF (153/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.12 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 5-49.
Table 5-49. Intel^® ICH3 Clock Inputs
Clock
Domain
Frequency Source
Usage
CLK66
66 MHz
Main Clock Should be running in all Cx states. Stopped in S3 ~ S5 based on
Generator SLP_S3# assertion.
PCICLK
33 MHz
Main Clock Free-running PCI Clock to ICH3. Stopped in S3 ~ S5 based on
Generator SLP_S3# assertion.
CLK48
48 MHz
Main Clock Used by USB Controllers. Stopped in S3 ~ S5 based on
Generator SLP_S3# assertion.
CLK14
14.318 MHz
Main Clock
Generator
Used by ACPI timers. Stopped in S3 ~ S5 based on SLP_S3#
assertion.
AC_BIT_CLK 12.288 MHz
AC ’97
Codec
AC ’97 Link. Control policy is determined by the clock source.
APICCLK
16.67 MHz
or 33 MHz
Main Clock
Generator
Used for ICH3-processor interrupt messages. Should be running
in C0, C1, and C2. Stopped in S3 ~ S5 based on SLP_S3#
assertion.
LAN_CLK
0.8 to 50
MHz
LAN
LAN Connect link. Control policy is determined by the clock
Connect source.
5.12.13 Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various hardware
mechanisms. ICH3 has a greatly simplified method for legacy power management compared with
previous generations, such as the PIIX4.
The scheme relies on the concept of detecting when individual subsystems are idle, detecting when
the whole system is idle, and detecting when accesses are attempted to idle subsystems.
However, the OS is assumed to be at least APM enabled. Without APM calls, there is no quick way
to know when the system is idle between keystrokes. The ICH3 does not support the burst modes
found in previous components (e.g., the PIIX4).
5.12.13.1 APM Power Management
The ICH3 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable
Register, will generate an SMI# once per minute. The SMI handler can check for system activity by
reading the DEVACT_STS Register. If none of the system bits are set, the SMI handler can
increment a software counter. When the counter reaches a sufficient number of consecutive
minutes with no activity, the SMI handler can then put the system into a lower power state.
If there is activity, various bits in the DEVACT_STS Register will be set. Software clears the bits
by writing a 1 to the bit position.
The DEVACT_STS Register allows for monitoring various internal devices, or Super I/O devices
(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.
Other PCI activity can be monitored by checking the PCI interrupts.
Intel^® 82801CA ICH3-S Datasheet
153