82801CA Datasheet, PDF (234/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register and Memory Mapping
Table 6-5. Memory Decode Ranges from Processor Perspective (Continued)
Memory Range
4 KB anywhere in 4 GB range
1 KB anywhere in 4 GB range
All other
Target
Dependency/Comments
Integrated LAN
Controller
IDE Expansion²
PCI
Enable via BAR in Device 29:Function 0 (Integrated
LAN Controller)
Enable via standard PCI mechanism and bits in
IDE I/O Configuration Register (Device 31, Function 1)
None
NOTES:
1. These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on PCI.
2. Software must not attempt locks to memory mapped I/O ranges for IDE Expansion. If attempted, the lock is
not honored, which means potential deadlock conditions may occur.
6.4.1 Boot-Block Update Scheme
The ICH3 supports a “top-block swap” mode that has the ICH3 swap the top block in the FWH (the
boot block) with another location. This allows for safe update of the Boot Block (even if a power
failure occurs). When the “top-swap” enable bit is set, the ICH3 will invert A16 for cycles targeting
FWH BIOS space. When this bit is 0, the ICH3 will not invert A16. This bit is automatically set to
0 by RTCRST#, but not by PCIRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block, and the block
immediately below the top block is reserved for doing boot-block updates.
The algorithm is:
1. Software copies the top block to the block immediately below the top.
2. Software checks that the copied block is correct. This could be done by performing a
checksum calculation.
3. Software sets the “top-block swap” bit. This will invert A16 for cycles going to the FWH.
Processor access to FFFF_0000 through FFFF_FFFF will be directed to FFFE_0000 through
FFFE_FFFF in the FWH, and processor accesses to FFFE_0000 through FFFE_FFFF will be
directed to FFFF_0000 through FFFF_FFFF.
4. Software erases the top block.
5. Software writes the new top block.
6. Software checks the new top block.
7. Software clears the top-block swap bit.
If a power failure occurs at any point after step 3, the system will be able to boot from the copy of
the boot block that is stored in the block below the top. This is because the top-swap bit is backed
in the RTC well.
Note: The top-block swap mode may be forced by an external strapping option (See Section 2.20.1).
When top-block swap mode is forced in this manner, the top-swap bit cannot be cleared by
software. A re-boot with the strap removed will be required to exit a forced top-block swap mode.
Note: The top-block swap mode only affects accesses to the FWH BIOS space, not feature space.
Note: The top-block swap mode has no effect on accesses below FFFE_0000h.
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Intel^® 82801CA ICH3-S Datasheet