82801CA Datasheet, PDF (175/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-59. TD Control and Status (Continued)
Bit
Description
22
21
20
19
18
17
16
15:11
10:0
Stalled.
1 = Set to a 1 by the ICH3 during status updates to indicate that a serious error has occurred at the
device/endpoint addressed by this TD. This can be caused by babble, the error counter counting
down to zero, or reception of the STALL handshake from the device during the transaction. Any
time that a transaction results in the stalled bit being set, the active bit is also cleared (set to 0).
If a STALL handshake is received from a SETUP transaction, a Time Out Error will also be
reported.
Data Buffer Error (DBE).
1 = Set to a 1 by the ICH3 during status update to indicate that the ICH3 is unable to keep up with
the reception of incoming data (overrun) or is unable to supply data fast enough during
transmission (underrun). When this occurs, the actual length and Max Length field of the TD will
not match. In the case of an underrun, the ICH3 will transmit an incorrect CRC (thus invalidating
the data at the endpoint) and leave the TD active (unless error count reached zero). If a overrun
condition occurs, the ICH3 will force a timeout condition on the USB, invalidating the transaction
at the source.
Babble Detected (BABD).
1 = Set to a 1 by the ICH3 during status update when “babble” is detected during the transaction
generated by this descriptor. Babble is unexpected bus activity for more than a preset amount of
time. In addition to setting this bit, the ICH3 also sets the” STALLED” bit (bit 22) to a 1. Since
”babble” is considered a fatal error for that transfer, setting the ”STALLED bit to a 1 insures that
no more transactions occur as a result of this descriptor. Detection of babble causes immediate
termination of the current frame. No further TDs in the frame are executed. Execution resumes
with the next frame list index.
Negative Acknowledgment (NAK) Received (NAKR).
1 = Set to a 1 by the ICH3 during status update when the ICH3 receives a “NAK” packet during the
transaction generated by this descriptor. If a NAK handshake is received from a SETUP
transaction, a Time Out Error will also be reported.
CRC/Time Out Error (CRC_TOUT).
1 = Set to a 1 by the ICH3 as follows:
During a status update in the case that no response is received from the target device/endpoint
within the time specified by the protocol chapter of the USB specification.
During a status update when a Cycli Redundancy Check (CRC) error is detected during the
transaction associated with this transfer descriptor.
In the transmit case (OUT or SETUP command), this is in response to the ICH3 detecting a
timeout from the target device/endpoint.
In the receive case (IN command), this is in response to the ICH3’s CRC checker circuitry
detecting an error on the data received from the device/endpoint or a NAK or STALL handshake
being received in response to a SETUP transaction.
Bit Stuff Error (BSE).
1 = This bit is set to a 1 by the ICH3 during status update to indicate that the receive data stream
contained a sequence of more than 6 ones in a row.
Bus Turn Around Time-out (BTTO).
1 = This bit is set to a 1 by the ICH3 during status updates to indicate that a bus time-out condition
was detected for this USB transaction. This time-out is specially defined as not detecting an
IDLE-to ‘K’ state Start of Packet (SOP) transition from 16 to 18 bit times after the SE0-to IDE
transition of previous End of Packet (EOP).
Reserved
Actual Length (ACTLEN). The Actual Length field is written by the ICH3 at the conclusion of a USB
transaction to indicate the actual number of bytes that were transferred. It can be used by the
software to maintain data integrity. The value programmed in this register is encoded as n-1 (see
Maximum Length field description in the TD Token).
Intel^® 82801CA ICH3-S Datasheet
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