82801CA Datasheet, PDF (304/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.2.11
DMA_WRMSK—DMA Write All Mask Register
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Fh;
Ch. #4–7 = DEh
0000 1111
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:4 Reserved. Must be 0.
Channel Mask Bits—R/W. This register permits all four channels to be simultaneously enabled/
disabled instead of enabling/disabling each channel individually, as is the case with the Mask
Register - Write Single Mask Bit. In addition, this register has a read path to allow the status of the
channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/
Word Count Register reaches terminal count (unless the channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the
corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0]
3:0 ^{indicate the DMA channel [3:0] ([7:4]) mask status.}
Bit 0 = Channel 0 (4) 1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5) 1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6) 1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7) 1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channels 0–3 through
channel 4.
304
Intel^® 82801CA ICH3-S Datasheet