82801CA Datasheet, PDF (97/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.5.2 PCI DMA Expansion Cycles
ICH3’s support of the PC/PCI DMA Protocol currently consists of four types of cycles: Memory to
I/O, I/O to Memory, Verify, and ISA Master cycles. ISA Masters are supported through the use of a
DMA channel that has been programmed for cascade mode.
The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA
“fly-by” cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory
read or memory write bus cycle, its address representing the selected memory.
The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses
(Table 5-10). Note that these cycles must be qualified by an active GNT# signal to the requesting
device.
Table 5-10. DMA Cycle vs. I/O Address
DMA Cycle Type
Normal
Normal TC
Verify
Verify TC
DMA I/O Address
00h
04h
0C0h
0C4h
PCI Cycle Type
I/O Read/Write
I/O Read/Write
I/O Read
I/O Read
5.5.3
DMA Addresses
The memory portion of the cycle will generate a PCI memory read or memory write bus cycle, its
address representing the selected memory. The I/O portion of the DMA cycle will generate a PCI
I/O cycle to one of the four I/O addresses listed in Table 5-10.
5.5.4 DMA Data Generation
The data generated by PC/PCI devices on I/O reads when they have an active GNT# is on the lower
two bytes of the PCI AD bus. Table 5-11 lists the PCI pins that the data appears on for 8- and 16-bit
channels. Each I/O read results in one memory write and each memory read results in one I/O
write. If the I/O device is 8 bit, the ICH3 performs an 8-bit memory write. The ICH3 does not
assemble the I/O read into a DWord for writing to memory. Similarly, the ICH3 does not
disassemble a DWord read from memory to the I/O device.
Table 5-11. PCI Data Bus vs. DMA I/O port size
PCI DMA I/O Port Size
Byte
Word
PCI Data Bus Connection
AD[7:0]
AD[15:0]
Intel^® 82801CA ICH3-S Datasheet
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