82801CA Datasheet, PDF (207/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.17.6.1 Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH3 SMBus Slave I/F. The
“command” field (bits 11–18) indicate which register is being accessed. The Data field
(bits 20–27) indicate the value that should be written to that register.
The Write Cycle format is shown below in Table 5-91. Table 5-92 has the values associated with
the registers.
Table 5-91. Slave Write Cycle Format
Bits
Description
1 Start Condition
2–8 Slave Address–7 bits
9 Write
10 ACK
11–18 Command
19 ACK
20–27 Register Data
28 ACK
29 Stop
Driven by
Comment
External Microcontroller
External Microcontroller
Must match value in Receive Slave Address
Register
External Microcontroller Always 0
ICH3
External Microcontroller
This field indicates which register will be
accessed.
See Table 5-92 below for the register
definitions
ICH3
External Microcontroller
See Table 5-92 below for the register
definitions
ICH3
External Microcontroller
Table 5-92. Slave Write Registers
Register
0
1–3
4
5
6–7
8
9–FFh
Function
Command Register. See Table 5-93 for legal values written to this register.
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored.
Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data
byte registers until they have been read by the system processor. The ICH3 will overwrite the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH3 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
Intel^® 82801CA ICH3-S Datasheet
207