82801CA Datasheet, PDF (370/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.13
SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1)
Address Offset: 14h–17h
Default Value:
00000001h
Attribute:
Size:
R/W
32 bits
Bit
31:16
15:2
1
0
Description
Reserved.
Base Address—R/W. Base address of the I/O space (4 consecutive I/O locations).
Reserved.
Resource Type Indicator (RTE)—This bit is set to one, indicating a request for I/O space.Read-
Only.
Note: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.
10.1.14
BM_BASE—Bus Master Base Address Register
(IDE—D31:F1)
Address Offset: 20h–23h
Default Value: 00000001h
Attribute:
Size:
R/W
32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16-byte I/O space
to provide a software interface to the Bus Master functions. Only 12 bytes are actually used
(6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address.
Bit
31:16
15:4
3:1
0
Description
Reserved.
Base Address—R/W. Base address of the I/O space (16 consecutive I/O locations).
Reserved.
Resource Type Indicator (RTE)—RO. Hardwired to 1, indicating a request for I/O space.
10.1.15 EXBAR—Expansion Base Address Register (IDE—D31:F1)
Address Offset: 24h–27h
Default Value: 00h
Attribute:
Size:
R/W
32 bits
Note: This is a memory mapped BAR that requires 1 KB of dword aligned memory that is Intel reserved
for future functionality. BIOS needs to program the base address for a 1-K memory space.
Bit
Description
31:0 Intel Reserved for Future Functionality.
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Intel^® 82801CA ICH3-S Datasheet