82801CA Datasheet, PDF (308/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.4
Intel^® 8259 Interrupt Controller (PIC) Registers
9.4.1 Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller (IRQ0–7), and
at A0h and A1h for the slave controller (IRQ8–13). These registers have multiple functions,
depending upon the data written to them. Below is a description of the different register
possibilities for each address.
Table 9-3. PIC Registers
Port
20h
21h
A0h
A1h
4D0h
4D1h
Aliases
Register Name
24h, 28h,
2Ch, 30h,
34h, 38h, 3Ch
Master PIC ICW1 Init. Cmd Word 1
Master PIC OCW2 Op Ctrl Word 2
Master PIC OCW3 Op Ctrl Word 3
25h, 29h,
2Dh, 31h,
35h, 39h, 3Dh
Master PIC ICW2 Init. Cmd Word 2
Master PIC ICW3 Init. Cmd Word 3
Master PIC ICW4 Init. Cmd Word 4
Master PIC OCW1 Op Ctrl Word 1
A4h, A8h,
ACh, B0h,
B4h, B8h, BCh
Slave PIC ICW1 Init. Cmd Word 1
Slave PIC OCW2 Op Ctrl Word 2
Slave PIC OCW3 Op Ctrl Word 3
A5h, A9h,
ADh, B1h,
B5h, B9h, BDh
Slave PIC ICW2 Init. Cmd Word 2
Slave PIC ICW3 Init. Cmd Word 3
Slave PIC ICW4 Init. Cmd Word 4
Slave PIC OCW1 Op Ctrl Word 1
–
Master PIC Edge/Level Triggered
–
Slave PIC Edge/Level Triggered
Default
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
00h
00h
Type
WO
WO
R/W
WO
WO
WO
R/W
WO
WO
R/W
WO
WO
WO
R/W
R/W
R/W
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Intel^® 82801CA ICH3-S Datasheet