82801CA Datasheet, PDF (168/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-55. Interrupt/Active Bit Interaction Definition
Interrupt
0
1
1
0
Active
Description
1
DMA transfer is in progress. No interrupt has been generated by the IDE device.
The IDE device generated an interrupt. The controller exhausted the Physical
0
Region Descriptors. This is the normal completion case where the size of the
physical memory regions was equal to the IDE device transfer size.
The IDE device generated an interrupt. The controller has not reached the end of the
1
physical memory regions. This is a valid completion case where the size of the
physical memory regions was larger than the IDE device transfer size.
This bit combination signals an error condition. If the error bit in the status register is
0
set, then the controller has some problem transferring data to/from memory.
Specifics of the error have to be determined using bus-specific information. If the
error bit is not set, then the PRD's specified a smaller size than the IDE transfer size.
5.15.2.5
5.15.2.6
Error Conditions
IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis;
either a sector is transferred successfully or it is not. A sector is 512 bytes.
If the IDE device does not complete the transfer due to a hardware or software error, the command
will eventually be stopped by the driver setting command start bit to zero when the driver times out
the disk transaction. Information in the IDE device registers help isolate the cause of the problem.
If the controller encounters an error while doing the bus master transfers, it will stop the transfer
(i.e., reset the active bit in the command register) and set the error bit in the Bus Master IDE Status
Register. The controller does not generate an interrupt when this happens. The device driver can
use device specific information (PCI configuration space status register and IDE drive register) to
determine what caused the error.
When a requested transfer does not complete properly, information in the IDE device registers
(Sector Count) can be used to determine how much of the transfer was completed and to construct
a new PRD table to complete the requested operation. In most cases the existing PRD table can be
used to complete the operation.
Intel^® 8237-Like Protocol
Intel 8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins
familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/write strobes.
These pins have similar characteristics to their ISA counterparts in terms of when data is valid
relative to strobe edges, and the polarity of the strobes, however the ICH3 does not use the 8237 for
this mode.
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Intel^® 82801CA ICH3-S Datasheet