82801CA Datasheet, PDF (383/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

USB 1.1 Controllers Registers
11.1.4
11.1.5
11.1.6
STA—Device Status Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
06–07h
0280h
Attribute:
Size:
R/WC
16 bits
Bit
Description
15:14 Reserved as 00b. Read Only.
Received Master Abort (RMA)—R/WC.
13 _{0 = Software clears this bit by writing a 1 to the bit location.}
1 = USB, as a master, generated a master-abort.
12 Reserved. Always read as 0.
Signaled Target Abort (STA)—R/WC.
11 _{0 = Software clears this bit by writing a 1 to the bit location.}
1 = USB function is targeted with a transaction that the ICH3 terminates with a target abort.
DEVSEL# Timing Status (DEV_STS)—RO. This 2-bit field defines the timing for DEVSEL#
10:9 assertion. These read only bits indicate the ICH3's DEVSEL# timing when performing a positive
decode. ICH3 generates DEVSEL# with medium timing for USB.
8 Data Parity Error Detected (DPED). Reserved as 0. Read Only.
7 Fast Back to Back (FB2B). Reserved as 1 Read Only.
6 User Definable Features (UDF). Reserved as 0. Read Only.
5 66 MHz Capable (66MHZ_CAP). Reserved as 0. Read Only.
4:0 Reserved.
RID—Revision Identification Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
08h
See Note
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 These bits contain device stepping information and are hardwired to the default value.
NOTE: Refer to the Specification Update for the Revision ID.
PI—Programming Interface Register (USB—D29:F0/F1/F2)
Address Offset:
09h
Default Value:
00h
Attribute:
Size:
RO
8 bits
Bit
Description
Programming Interface Value—RO:
7:0
00h = No specific register level programming interface defined.
Intel^® 82801CA ICH3-S Datasheet
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