82801CA Datasheet, PDF (489/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Testability
In this example, Vector 1 applies all 0s to the chain inputs. The outputs being non-inverting, will
consistently produce a 1 at the XOR output on a good board. One short to Vcc (or open floating to
Vcc) will result in a 0 at the chain output, signaling a defect.
Likewise, applying Vector 7 (all 1s) to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a 1 at the XOR chain output on a good board.
One short to Vss (or open floating to Vss) will result in a 0 at the chain output, signaling a defect. It
is important to note that the number of inputs pulled to 1 will affect the expected chain output
value. If the number of chain inputs pulled to 1 is even, then expect 1 at the output. If the number of
chain inputs pulled to 1 is odd, expect 0 at the output.
Continuing with the example in Table 18-2, as the input pins are driven to 1 across the chain in
sequence, the XOR Output will toggle between 0 and 1. Any break in the toggling sequence (e.g.,
1011) will identify the location of the short or open.
Table 18-3. XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks While PWROK Active)
Pin Name
AC_SYNC
AC_SDOUT
PIRQE#/GPIO2
GNTA#/GPIO16
PIRQH#/GPIO5
PIRQF#/GPIO3
PIRQG#/GPIO4
GNT3#
GNT0#
GNT4#
REQA#/GPIO0
REQB#/REQ5#/
GPIO1
REQ2#
GNTB#/GNT5#/
GPIO17
PIRQD#
PIRQC#
PIRQA#
PIRQB#
GNT2#
REQ0#
AD28
GNT1#
REQ4#
AD26
AD30
Ball #
A7
C7
A6
B6
A5
B5
C5
D5
A4
B4
C4
Notes
Top of XOR Chain
2nd signal in XOR
D4
A3
B3
A2
B2
B1
C1
D2
D3
D1
E3
E4
E2
E1
Pin Name
AD16
REQ1#
AD24
AD22
FRAME#
PAR
AD18
AD9
AD20
AD4
AD11
AD6
STOP#
TRDY#
AD2
AD13
AD0
AD15
C/BE1#
AD5
AD3
C/BE0#
AD1
SERR#
AD10
AC_SDIN1
Ball #
F5
F4
F3
F2
F1
G5
G4
G2
G1
H5
H4
H3
H2
H1
J4
J3
J2
J1
K5
K4
K3
K2
K1
L5
L4
C11
Notes
XOR Chain #1
OUTPUT
Intel^® 82801CA ICH3-S Datasheet
489