82801CA Datasheet, PDF (353/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.9.3
9.9.4
9.9.5
TCO1_TMR—TCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
TCOBASE +01h
0004h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:6 Reserved.
Value that is loaded into the timer each time the TCO_RLD register is written. Values of 0h–3h will
5:0 be ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and
this allows timeouts ranging from 2.4 seconds to 38 seconds.
TCO1_DAT_IN—TCO Data In Register
I/O Address:
Default Value:
Lockable:
TCOBASE +02h
0000h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:0
Data Register for passing commands from the OS to the SMI handler. Writes to this register will
cause an SMI and set the OS_TCO_SMI bit in the TCO_STS register.
TCO1_DAT_OUT—TCO Data Out Register
I/O Address:
Default Value:
Lockable:
TCOBASE +03h
0000h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
Data Register for passing commands from the SMI handler to the OS. Writes to this register will set
7:0 the TCO_INT_STS bit in the TCO_STS register. It will also cause an interrupt, as selected by the
TCO_INT_SEL bits.
Intel^® 82801CA ICH3-S Datasheet
353