82801CA Datasheet, PDF (34/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Introduction
LAN Controller
The ICH3’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high-
level commands and perform multiple operations; this lowers processor utilization by off-loading
communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help
prevent data underruns and overruns while waiting for bus accesses. This enables the integrated
LAN Controller to transmit data with minimum interframe spacing (IFS).
The LAN Controller can operate in either full duplex or half duplex mode. In full duplex mode the
LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half duplex
performance is enhanced by a proprietary collision reduction mechanism. See Section 5.2, “LAN
Controller (B1:D8:F0)” on page 5-71 for details.
RTC
The ICH3 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of
battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of
day and storing system data, even when the system is powered down. The RTC operates on a
32.768 KHz crystal and a separate 3 V lithium battery that provides up to seven years of protection.
The RTC also supports two lockable memory ranges. By setting bits in the configuration space,
two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of
passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in
advance, rather than just 24 hours in advance.
GPIO
Various general purpose inputs and outputs are provided for custom system design. The number of
inputs and outputs varies depending on ICH3 configuration.
Enhanced Power Management
The ICH3’s power management functions include enhanced clock control, local and global
monitoring support for 14 individual devices, and various low-power (suspend) states
(e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit
permits software-independent entrance to low-power states. The ICH3 contains full support for the
Advanced Configuration and Power Interface (ACPI) Specification.
System Management Bus (SMBus 2.0)
The ICH3 contains an SMBus Host interface that allows the processor to communicate with
SMBus slaves. This interface is compatible with most I²C devices. Special I²C commands are
implemented.
The ICH3’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the ICH3 supports slave functionality,
including the Host Notify protocol. Hence, the host controller supports 8 command protocols of the
SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick
Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block
Read/Write, and Host Notify.
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Intel^® 82801CA ICH3-S Datasheet